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integrated circuit systems, inc. ics9248-185 block diagram pentium is a trademark of intel corporation i 2 c is a trademark of philips corporation frequency generator & integrated buffers for pentium/pro tm & k6 9248-185 reve- 12/15/08 pin configuration 28-pin ssop/tssop * internal pull-up resistor of 120k to vdd 1. these pin will have 2x drive strength 2. fs1 is a pull down recommended application: via pm133 chipset output features: ? 2 - cpus @ 2.5v 5 - sdram @ 3.3v 3 - pci @ 3.3v, 1 - 48mhz, @ 3.3v fixed. 2 - ref @ 3.3v, 14.318mhz. features: up to 133mhz frequency support support power management: pci_stop & clk_stop spread spectrum for emi control (-0.5% down spread). uses external 14.318mhz crystal fs pins for frequency select key specifications: cpu ? pci skew: 1-4ns pci ? pci skew: 500ps cpu ? cpu skew: 175ps cpu jitter: 250ps (cyc-cyc) pci jitter: 500ps (cyc-cyc) buffer_in pll2 pll1 spread spectrum 48mhz cpuclk1 sdram (4:1) pciclk (1:0) 2 2 4 sdram0/_f cpuclk0/_f pciclk_f x1 x2 xtal osc cpu divder pci divder stop stop stop pci_stop# clk_stop# fs (1:0) control logic config. reg. ref (1:0) frequency select vdd ref0 gnd x1 x2 vddpci *pciclk_f gnd fs1/pciclk0 buffer_in pciclk1 pci_stop# gnd *fs0/48mhz 1 1, 2 1 ref1/free_sel* vddl cpuclk0/_f cpuclk1 gnd clk_stop# sdram0/_f sdram1 sdram2 gnd vddsdr sdram3 sdram4 vdd48 1 ics9248-185 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 s f0 s fk l c u p ck l c i c p n w o d d a e r p s 00 6 6 . 6 63 3 . 3 3% 5 . 0 - 01 0 0 . 0 0 13 3 . 3 3% 5 . 0 - 10 0 0 . 7 93 3 . 2 3% 5 . 0 - 11 3 3 . 3 3 13 3 . 3 3% 5 . 0 - ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
2 ics9248-185 pin descriptions notes: 1: internal pull-up resistor of 120k to 3.3v on indicated inputs 2: bidirectional input/output pins, input logic levels are latched at internal power-on-reset. use 10kohm resistor to program logic hi to vdd or gnd for logic low. general description the ics9248-185 is the single chip clock solution for notebook designs using the 440bx or the via apollo pro 133 style chipset. it provides all necessary clock signals for such a system. the ics9248-185 provides cpu and pci clocks with continous spread spectrum. the ics9248-185 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. n i p r e b m u n e m a n n i pe p y tn o i t p i r c s e d , 8 1 , 5 1 , 6 , 1d d vr w pv 3 . 3 l a n i m o n , y l p p u s r e w o p 20 f e rt u o r e f f u b r e g n o r t s e h t s i t u p t u o f e r s i h t . k c o l c e c n e r e f e r z h m 8 1 3 . 4 1 s d a o l s u b a s i r o f , 3 1 , 8 , 3 4 2 , 9 1 d n gr w pd n u o r g 41 xn i 2 x m o r f r o t s i s e r k c a b d e e f d n a ) f p 6 3 ( p a c d a o l l a n r e t n i s a h , t u p n i l a t s y r c 52 xt u o. z h m 8 1 3 . 4 1 y l l a n i m o n , t u p t u o l a t s y r c 7f _ k l c i c pt u o . t n e m e g a n a m r e w o p r o f # p o t s _ i c p y b d e t c e f f a t o n k c o l c i c p g n i n n u r e e r f 9 1 s f 2 , 1 n i. t u p n i d e h c t a l . n i p t c e l e s y c n e u q e r f 0 k l c i c pt u o ) y l r a e u p c ( w e k s s n 4 - 1 h t i w s k c o l c u p c o t s u o n o r h c n y s . t u p t u o k c o l c i c p 0 1n i r e f f u bn i. s t u p t u o m a r d s r o f s r e f f u b t u o n a f o t t u p n i 1 11 k l c i c pt u o ) y l r a e u p c ( w e k s s n 4 - 1 h t i w s k c o l c u p c o t s u o n o r h c n y s . t u p t u o k c o l c i c p 2 1# p o t s _ i c pn i w o l t u p n i n e h w , l e v e l 0 c i g o l t a s k c o l c k l c i c p s t l a h ) 0 = e d o m , e d o m e l i b o m n i ( 4 1 0 s f 2 , 1 n it u p n i d e h c t a l . n i p t c e l e s y c n e u q e r f z h m 8 4t u ok c o l c t u p t u o z h m 8 4 , 0 2 , 7 1 , 6 1 1 2 ) 1 : 4 ( m a r d st u o n i p n i r e f f u b m o r f s t u p t u o r e f f u b t u o n a f , s t u p t u o k c o l c m a r d s . ) t e s p i h c y b d e l l o r t n o c ( 2 2f _ / 0 m a r d st u ol e s _ e e r f n o g n i d n e p e d e l b a p p o t s r o m a r d s g n i n n u r e e r f r e h t i e 3 2# p o t s _ k l cn i l e v e l " 0 " c i g o l t a s m a r d s & , s k l c u p c s t l a h t u p n i s u o n o r h c n y s a s i h t . w o l n e v i r d n e h w 5 21 k l c u p ct u ol d d v y b d e r e w o p , t u p t u o k c o l c u p c 6 2f _ / 0 k l c u p ct u ol e s _ e e r f n o g n i d n e p e d e l b a p p o t s r o k l c u p c g n i n n u r e e r f r e h t i e 7 2l d d vr w pv 5 . 2 s k c o l c u p c r o f y l p p u s 8 2 l e s _ e e r fn i r o g n i n n u r e e r f r e h t i e e b o t f _ / 0 m a r d s d n a f _ / 0 k l c u p c s t c e l e s e v o b a e h t w o l ) 0 ( o t t e s s i l e s _ e e r f n e h w . # p o t s _ k l c y b e l b a p p o t s . e l b a p p o t s e r a s k c o l c e h t , h g i h ) 1 ( o t t e s n e h w - g n i n n u r e e r f e r a s k c o l c 1 f e rt u o. k c o l c e c n e r e f e r z h m 8 1 3 . 4 1
3 ics9248-185 electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2v dd +0.3 v input low voltage v il v ss -0.3 0.8 v c l = 30 pf; select @ 66mhz 63 150 c l = 30 pf; select @ 100mhz 67 170 c l = 30 pf; select @ 133mhz 73 180 powerdown current i ddpd cl = 0 pf; input address vdd or gnd 600 a input frequency f i v dd = 3.3 v 12 14.318 16 mhz input capacitance 1 c in logic inputs 5 pf c inx x1 & x2 pins 27 36 45 pf clk stabilization 1 t stab from v dd = 3.3 v to 1% target freq. 5.5 ms skew 1 t cpu-pci1 v t = 1.5 v 1284ns 1 guaranteed by design, not 100% tested in production. ma operating supply current i dd3.3op absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . 0c to +70c case temperature . . . . . . . . . . . . . . . . . . . . . . . . 115c storage temperature . . . . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operation al sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability.
4 ics9248-185 electrical characteristics - cpu t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 20 pf parameter symbol conditions min typ max units output high voltage v oh2a i oh = -20 ma 2.4 2.85 v output low voltage v ol2a i o l = 12 ma 0.31 0.4 v output high current i oh2a v oh = 2.0 v -45 -27 ma output low current i ol2a v ol = 0.8 v 22 29 ma rise time 1 t r2a v ol = 0.4 v, v oh = 2.4 v 0.9 1.6 ns fall time 1 t f2a v oh = 2.4 v, v ol = 0.4 v 1 1.6 ns duty cycle 1 d t2a v t = 1.5 v 45 50 55 % skew window 1 t sk2a v t = 1.5 v 35 175 ps jitter, cycle-to-cycle 1 t j c y c-c y c2a v t = 1.5 v dram not running, cpu=66.6mhz 123 150 ps jitter, cycle-to-cycle 1 t jcyc-cyc2a v t = 1.5 v dram running 119 250 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - cpu t a = 0 - 70c; vddl= 2.5v, +/-5%; c l = 20 pf parameter symbol c onditions min typ max units output high voltage v oh2a i oh = -20 ma 2 2.3 v output low voltage v ol2a i ol = 12 ma 0.31 0.4 v output high current i oh2a v oh = 2.0 v -39 -21 ma output low current i ol2a v ol = 0.8 v 22 26 ma rise time 1 t r2a v ol = 0.4 v, v oh = 2.0 v 0.96 1.6 ns fall time 1 t f2a v oh = 2.0 v, v ol = 0.4 v 1.06 1.6 ns duty cycle 1 d t2a v t = 1.25 v 45 50.3 55 % skew window 1 t sk2a v t = 1.25 v 35 175 ps jitter, cycle-to-cycle 1 t j c y c-c y c2a v t = 1.25 v dram not running 123 150 ps jitter, cycle-to-cycle 1 t jcyc-cyc2a v t = 1.25 v dram running 119 250 ps 1 guaranteed b y desi g n, not 100% tested in production.
5 ics9248-185 electrical characteristics - pci t a = 0 - 70c; v dd = 3.3 v , vddl = 2.5v, +/-5%; c l = 30 pf parameter symbol c onditions min typ max units output high voltage v oh1 i oh = -18 ma 2.4 3 v output low voltage v ol1 i ol = 9.4 ma 0.2 0.4 v output high current i oh1 v oh = 2.0 v -62 -33 ma output low current i ol1 v ol = 0.8 v 38 43 ma rise time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 1.51 2 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 1.47 2 ns duty cycle 1 d t1 v t = 1.5 v 45 50.1 55 % skew window 1 t sk1 v t = 1.5 v 58 500 ps jitter, cycle to cycle t cycle v t = 1.5 v 145 500 ps 1 guaranteed b y desi g n, not 100% tested in production. electrical characteristics - sdram t a = 0 - 70c; v dd = 3.3 v, vddl= 2.50v, +/-5%; c l = 30 pf parameter symbol conditions min typ max units output high voltage v oh3 i oh = -28 ma 2.4 3 v output low voltage v ol3 i ol = 19 ma 0.3 0.4 v output high current i oh3 v oh = 2.0 v -69 -46 ma output low current i ol3 v ol = 0.8 v 32 42 ma rise time 1 t r3 v ol = 0.4 v, v oh = 2.4 v 1.07 1.3 ns fall time 1 t f3 v oh = 2.4 v, v ol = 0.4 v 1.3 2 ns duty cycle 1 d t3 v t = 1.5 v 45 50.8 55 % skew window 1 t sk3 v t = 1.5 v 104 250 ps propagation time 1 (buffer in to output) t sk3 v t = 1.5 v 5ns 1 guaranteed by design, not 100% tested in production.
6 ics9248-185 electrical characteristics - ref t a = 0 - 70c; v dd = 3.3 v, vddl= 2.5v +/-5%; c l = 10 - 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh5 i oh = -14 ma 2.4 2.6 v output low voltage v ol5 i o l = 6 ma 0.22 0.4 v output high current i oh5 v oh = 2.0 v -32 -20 ma output low current i ol5 v ol = 0.8 v 16 22 ma rise time 1 t r5 v ol = 0.4 v, v oh = 2.4 v 2.11 4 ns fall time 1 t f5 v oh = 2.4 v, v o l = 0.4 v 2.14 4 ns duty cycle 1 d t5 v t = 1.5 v 45 52.1 55 % jitter, cycle to cycle 1 t jcycle5 v t = 1.5 v -600 848 1000 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - 48mhz t a = 0 - 70c; v dd = 3.3 v, vddl= 2.5v +/-5%; c l = 10 - 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh5 i oh = -14 ma 2.4 2.6 v output low voltage v ol5 i ol = 6 ma 0.22 0.4 v output high current i oh5 v oh = 2.0 v -32 -20 ma output low current i ol5 v ol = 0.8 v 16 22 ma rise time 1 t r5 v ol = 0.4 v, v oh = 2.4 v 1.79 4 ns fall time 1 t f5 v oh = 2.4 v, v ol = 0.4 v 1.92 4 ns duty cycle 1 d t5 v t = 1.5 v 45 50.8 55 % jitter, cycle to cycle t jcycle v t = 1.5 v 267 500 ps 1 guaranteed b y desi g n, not 100% tested in production.
7 ics9248-185 clk_stop# timing diagram clk_stop# is an asychronous input to the clock synthesizer. it is used to turn off the cpu clocks for low power operation. clk_stop# is synchronized by the ics9248-185 . the minimum that the cpu clock is enabled (clk_stop# high pulse) is 100 cpu clocks. all other clocks will continue to run while the cpu clocks are disabled. the cpu clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. cpu clock on latency is less than 4 cpu clocks and cpu clock off latency is less than 4 cpu clocks. notes: 1. all timing is referenced to the internal cpu clock. 2. clk_stop# is an asynchronous input and metastable conditions may exist. this signal is synchronized to the cpu clocks inside the ics9248-185. 3. all other clocks continue to run undisturbed. pciclk sdram cpuclk cpuclk _f sdram_f pci_stop# (high) clk_stop# internal cpuclk
8 ics9248-185 pci_stop# timing diagram pci_stop# is an asynchronous input to the ics9248-185 . it is used to turn off the pciclk clocks for low power operation. pci_stop# is synchronized by the ics9248-185 internally. the minimum that the pciclk clocks are enabled (pci_stop# high pulse) is at least 10 pciclk clocks. pciclk clocks are stopped in a low state and started with a full high pulse width guaranteed. pciclk clock on latency cycles are only three rising pciclk clocks, off latency is one pciclk clock. notes: 1. all timing is referenced to the internal cpuclk (defined as inside the ics9248 device.) 2. pci_stop# is an asynchronous input, and metastable conditions may exist. this signal is required to be synchronized inside the ics9248. 3. all other clocks continue to run undisturbed. 4. clk_stop# is shown in a high (true) state. cpuclk (internal) pciclk_f (internal) pciclk_f (free-running) clk_stop# pciclk [6:0] pci_stop#
9 ics9248-185 fig. 1 shared pin operation - input/output pins the i/o pins designated by (input/output) serve as dual signal functions to the device. during initial power-up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. at the end of power-on reset, (see ac characteristics for timing values), the device changes the mode of operations for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm (10k) resistor is used to provide both the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. via to vdd clock trace to load series term. res. programming header via to gnd device pad 2k 8.2k figure 1 shows a means of implementing this function when a switch or 2 pin header is used. with no jumper is installed the pin will be pulled high. with the jumper in place the pin will be pulled low. if programmability is not necessary, than only a single resistor is necessary. the programming resistors should be located close to the series termination resistor to minimize the current loop area. it is more important to locate the series termination resistor close to the driver than the programming resistor.
10 ics9248-185 seating plane seating plane a1 a a2 e -c- - c - b .10 (.004) c .10 (.004) c c l index area index area 12 1 2 n d e1 e 209 mil ssop min max min max a--2.00--.079 a1 0.05 -- .002 -- a2 1.65 1.85 .065 .073 b 0.22 0.38 .009 .015 c 0.09 0.25 .0035 .010 d e 7.40 8.20 .291 .323 e1 5.00 5.60 .197 .220 e l 0.55 0.95 .022 .037 n 0 8 0 8 variations min max min max 28 9.90 10.50 .390 .413 10-0033 symbol in millimeters in inches common dimensions common dimensions see variations see variations 0.65 basic 0.0256 basic reference doc.: jedec publication 95, mo-150 see variations see variations n d mm. d (inch) ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ordering information 9248 y f-185lft designation for tape and reel packaging lead free, rohs compliant pattern number (2 or 3 digit number for parts with rom code patterns) package type f = ssop revision designator (will not correlate with datasheet revision) device type example: xxxx y f - ppp lf t
11 ics9248-185 4.40 mm. body, 0.65 mm. pitch tssop (173 mil) (0.0256 inch) index area index area 12 1 2 n d e1 e seating plane seating plane a1 a a2 e -c- - c - b c l aaa c min max min max a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.19 0.30 .007 .012 c 0.09 0.20 .0035 .008 d e e1 4.30 4.50 .169 .177 e l 0.45 0.75 .018 .030 n 0 8 0 8 aaa -- 0.10 -- .004 v ariations min max min max 28 9.60 9.80 .378 .386 10-0035 n d mm. d ( inch ) reference doc.: jedec publication 95, mo-153 0.65 basic 0.0256 basic see variations see variations see variations see variations 6.40 basic 0.252 basic symbol in millimeters in inches common dimensions common dimensions ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ordering information 9248 y g-185lft designation for tape and reel packaging lead free, rohs compliant pattern number (2 or 3 digit number for parts with rom code patterns) package type g = tssop revision designator (will not correlate with datasheet revision) device type example: xxxx y g - ppp lf t
12 ics9248-185 revision history rev. issue date description page # d 10/7/2008 added lf ordering information. 10-11 e 12/15/2008 removed ics prefix from ordering information. 10-11

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